Many devices, particularly handheld devices, are required to operate for long periods of time on battery power. To do this, such devices often support one or more lower power modes of operation, such as while waiting to receive a message or phone call. During such times, various parts of these devices may be put into a low power mode that reduces their power consumption.
Many of these devices are built using one or more integrated circuits that are often made of Complementary Metal-Oxide Semiconductor (CMOS) transistors. The transistors tend to be used in two distinct kinds of circuits, often known as digital and analog circuits. This patent application will focus on digital circuits that tend to operate on signals coded as 0's and 1's, which are often referred to as bits.
Logic circuits are frequently composed of logic cells that may store bits and/or operate on bits. The logic cells are often part of a library of cells that have been designed, not only electrically, but also as layout templates, simulated, verified and tested for the specific semiconductor manufacturing process for the intended integrated circuit.
Examples of logic cells often found in cell libraries include, but are not limited to, logic gates and latches. Examples of logic gates include nand and nor gates. A nand gate forms the logic complement of the conjunction of two or more inputs, so that a two input nand gate may receive two logical inputs and generate an output which is ‘1’ when either input is ‘0’, and generate an output of ‘0’ when both inputs are ‘1’. A nor gate with two inputs generates an output of ‘1’ when both inputs are ‘0’ and an output of ‘0’ when at least one input is ‘1’.
Logic latches tend to maintain an internal state that forms their output. Examples of latches include D flip-flops and R-S latches. The D flip-flop receives a clock signal and a data signal, and the internal state changes by capturing the data signal at a transition of the clock signal. An R-S (Reset-Set) latch receives a reset signal and a set signal, and operates under the condition that both the reset and set signal are not both asserted (set to ‘1’) at the same time. When the reset signal is asserted, the internal state is set to ‘0’. When the set signal is asserted, the internal state is set to 1. Some logic latches may have outputs that are further conditioned or gated.
Reducing leakage current in low power mode operations of integrated circuits extends the battery life of the devices using these integrated circuits. In the prior art, the leakage current may be reduced using specialized latches that receive a specialized power control signal, placing them in the low power mode, and enabling output of a lower power setting that reduces the leakage current during low power mode in the integrated circuit logic cells.
CMOS transistors typically include three electrical terminals, known as the source, gate and drain. The threshold voltage of a CMOS transistor may be considered to be the voltage at the gate that causes a low resistance path to form between the source and the drain. To reduce power consumption during their active modes, CMOS transistors may be built with reduced load capacitance and threshold voltages. However, this can increase leakage power dissipation due to an increase in sub-threshold leakage currents, particularly in low power mode.
These problems generally arise after the design and manufacturing and before even one of the integrated circuit and the devices using these integrated circuits make any revenue for their manufacturer. There are other problems with this approach that affect the time from the start of design until revenue generation begins, which is known as the time to market. The prior art approach has several other problems in this context including but not limited to the following.
First, use of a specialized latch and/or flip-flop requires adding these cells to the cell library available to design the integrated circuit. This adds to the circuit design, simulation and verification overhead for the cell library, and requires characterization of these cells in the manufacturing process for the integrated circuit. Each and all of these steps cost money and increase the time to market for the integrated circuit and the device that uses it.
Second, these specialized latches and/or flip-flops may be larger than the corresponding cells of the existing cell libraries.
Third, these specialized cells tend to have added drive capacitance during normal operations, consuming more power and possibly reducing performance.
Fourth, the low leakage state is built into these special cells, often leading to no way to fix a bug without a new round of silicon, which is extremely expensive.
And fifth, these specialized circuits are often challenging to fully test due to their added complexity.
These problems translate into added costs throughout the design, prototype and production phases of such integrated circuits while often increasing the critical path for the time to market for the devices using these integrated circuits.
Mechanisms and methods are needed that address at least some of these problems.